F
fetch pipeline [1] [2]
fetching, an instruction
FGR (Floating-Point General register)
32-bit operations
5-bit select
64-bit operations
load operations
operations
Status register FR bit
store operations
Flag, field (FP)
flag
uncorrectable error
Floating-Point exception
Floating-Point Status register see also FSR
Floating-Point Unit, see also FPU
floating-point
divide
multiplier
pipeline
queue
registers
adder
adder pipeline
divide
queue
instructions written each cycle
number of allowable entries
ports
sequencing
rounding mode
square root
flow control
external data response
external request
processor coherency data response
processor eliminate request
processor read request
processor upgrade request
processor write request
format, TLB entry
FPU
Active List, control of FSR
add unit
arithmetic instructions
cause bits, FSR
changing rounding mode using a CTC1
compare
condition bits
control registers
divide unit
FGRs (general registers)
FSR, (Status register in FPU)
graduation, control of FSR
instructions, processor specific
latency
logic diagram
move to floating-point
multiply unit
operations
queue
controlling units
move unit, FPU
read ports
register file
repeat rate
rounding modes
serial dependency circuit
square-root unit
FrameMask register [1] [2]
free list
freeing the request number, with completion response
FSR (Floating-Point Status register)
cause bits
condition bits
division by zero
enable bits
flag bits
inexact result
invalid operation
load exceptions
loading the FSR
overflow
RM, round to minus infinity
RN, round to nearest representable value
RP, round to plus infinity
RZ, round toward zero
underflow
unimplemented operation
functional unit
branch
floating-point adder
floating-point multiplier
instruction decode and rename
iterative
Load/Store Unit
integer ALU